1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a bit line.
2. Description of the Related Art
In the design of Ultra Large Scale Integration (ULSI) DRAM, the lithography and alignment controlling the contact are increasingly critical as the device size is gradually reduced. When the photolithography step is performed to define a node contact hole, the node contact hole must align with the source/drain region. The larger the node contact hole is, the less tolerance for the contact hole the source/drain region has. The lower tolerance of the source/drain for the node contact hole results in the decrease of the alignment accuracy. Accordingly, the node contact is easily electrically coupled to the bit line surrounding the node contact, and this causes device failure.
FIGS. 1A through 1C are schematic, cross-sectional views of the conventional process for manufacturing a bit line.
As shown in FIG. 1A, a dielectric layer 104 is formed on a substrate 100 having a field effective transistor (FET) 102 on the substrate 100. A contact hole 108 is formed in the dielectric layer 104 and exposes a source/drain region 106. A polysilicon layer 110 is formed on the dielectric layer 104 and fills the contact hole 108.
As shown in FIG. 1B, the polysilicon layer is patterned to form a bit line 112. At this point, the bit line 112 process is finished.
As shown in FIG. 1C, after the process of fabricating a bit line of DRAM is finished, a dielectric layer 114 is formed over the substrate 100. A node contact hole 116 is formed in the dielectric layer 114 and exposes the source/drain region 106. A capacitor 118 is formed to electrically couple to the source/drain region 106 through the node contact hole 116.
As the integration of the integrated circuit increases and the density of the device in a wafer correspondingly increases, the process for manufacturing the node contact hole 116 mentioned above has a problem with the inadequate alignment margin between the node contact hole 116 and the bit line 112. Conventionally, the problem of the inadequate alignment margin can be solved by decreasing the width of the bit line. However, the method of decreasing the width of the bit line is limited by the resolution of the photolithography. Moreover, since the resistance of the bit line increases as the width of the bit line is decreased, it adversely affects DRAM operating at high speeds.